? semiconductor components industries, llc, 2012 april, 2013 ? rev. 3 1 publication order number: nb7l72m/d nb7l72m 2.5v / 3.3v differential 2 x 2 crosspoint switch with cml outputs clock/data buffer/translator multi ? level inputs w/ internal termination description the nb7l72m is a high bandwidth, low voltage, fully differential 2 x 2 crosspoint switch with cml outputs. the nb7l72m design is optimized for low skew and minimal jitter as it produces two identical copies of clock or data operating up to 7 ghz or 10 gb/s, respectively. as such, the nb7l72m is ideal for sonet, gige, fiber channel, backplane and other clock/data distribution applications. the differential in/in inputs incorporate internal 50 termination resistors and will accept lvpecl, cml, or lvds logic levels (see figure 11). the 16 ma differential cml outputs provide matching internal 50 terminations and produce 400 mv output swings when externally terminated with a 50 resistor to v cc (see figure 9). the nb7l72m is the 2.5 v/3.3 v v ersion of the and nb7v72m and is offered in a low profile 3x3 mm 16 ? pin qfn package. application notes, models, and support documentation are available at www.onsemi.com. the nb7l72m is a member of the gigacomm ? family of high performance clock products. features ? maximum input data rate > 10 gb/s ? data dependent jitter < 10 ps pk ? pk ? maximum input clock frequency > 7 ghz ? random clock jitter < 0.5 ps rms, max ? 150 ps typical propagation delay ? 30 ps typical rise and fall times ? differential cml outputs, 400 mv peak ? to ? peak, typical ? operating range: v cc = 2.375 v to 3.6 v with gnd = 0 v ? internal 50 input termination resistors ? qfn ? 16 package, 3mm x 3mm ? ? 40 c to +85 c ambient operating temperature ? these are pb ? free devices a = assembly location l = wafer lot y = year w = work week = pb ? free package (note: microdot may be in either location) *for additional marking information, refer to application note and8002/d. marking diagram* qfn ? 16 mn suffix case 485g http://onsemi.com see detailed ordering and shipping information in the package dimensions section on page 7 of this data sheet. ordering information in0 sel0 sel1 in0 + + vt0 in1 in1 vt1 q0 q0 q1 q1 0 1 0 1 figure 1. logic diagram 1 nb7l 72m alyw
nb7l72m http://onsemi.com 2 vt1 sel1 gnd vcc vt0 sel0 gnd vcc q0 q0 q1 q1 in0 in0 in1 in1 5678 16 15 14 13 12 11 10 9 1 2 3 4 nb7l72m exposed pad (ep) figure 2. pin configuration (top view) table 1. input/output select truth table sel0* sel1* q0 q1 l l in0 in0 l h in0 in1 h l in1 in0 h h in1 in1 *defaults high when left open table 2. pin description pin name i/o description 1 in0 lvpecl, cml, lvds input noninverted differential input. (note 1) 2 in0 lvpecl, cml, lvds input inverted differential input. (note 1) 3 in1 lvpecl, cml, lvds input inverted differential input. (note 1) 4 in1 lvpecl, cml, lvds input noninverted differential input. (note 1) 5 vt1 ? internal 50 termination pin for in1 and in1 . 6 sel1 lvcmos input input select logic pin for in0 or in1 inputs to q1 output. see table 1, input/output select truth table; pin defaults high when left open. 7 gnd negative supply voltage 8 vcc ? positive supply voltage 9 q1 cml output noninverted differential output. (note 1) 10 q1 cml output inverted differential output. (note 1) 11 q0 cml output inverted differential output. (note 1) 12 q0 cml output noninverted differential output. (note 1) 13 vcc ? positive supply voltage 14 gnd ? negative supply voltage 15 sel0 lvcmos input input select logic pin for in0 or in1 inputs to q0 output. see table 1, input/output select truth table; pin defaults high when left open. 16 vt0 ? internal 50 termination pin for in0 and in0 ? ep ? the exposed pad (ep) on the qfn ? 16 package bottom is thermally connected to the die for improved heat transfer out of package. the exposed pad must be attached to a heat ? sinking conduit. the pad is electrically connected to the die, and is recommended to be electrically and thermally connected to gnd on the pc board. 1. in the differential configuration when the input termination pins (vt0, vt1) are connected to a common termination voltage or left open, and if no signal is applied on inx/inx input, then the device will be susceptible to self ? oscillation. 2. all vcc and gnd pins must be externally connected to a power supply for proper operation.
nb7l72m http://onsemi.com 3 table 3. attributes characteristics value esd protection human body model machine model > 4 kv > 200 v r pu ? input pullup resistor 75 k moisture sensitivity (note 3) qfn ? 16 level 1 flammability rating oxygen index: 28 to 34 ul 94 v ? 0 @ 0.125 in transistor count 212 meets or exceeds jedec spec eia/jesd78 ic latchup test 3. for additional information, see application note and8003/d. table 4. maximum ratings symbol parameter condition 1 condition 2 rating unit v cc positive power supply gnd = 0 v 4.0 v v in positive input voltage gnd = 0 v ? 0.5 to v cc +0.5 v v inpp differential input voltage |in ? in | 1.89 v i in input current through r t (50 resistor) 40 ma i out output current through r t (50 resistor) 40 ma t a operating temperature range ? 40 to +85 c t stg storage temperature range ? 65 to +150 c ja thermal resistance (junction ? to ? ambient) (note 4) 0 lfpm 500 lfpm qfn ? 16 qfn ? 16 42 35 c/w c/w jc thermal resistance (junction ? to ? case) (note 4) qfn ? 16 4 c/w t sol wave solder pb ? free 265 c stresses exceeding maximum ratings may damage the device. maximum ratings are stress ratings only. functional operation above t he recommended operating conditions is not implied. extended exposure to stresses above the recommended operating conditions may af fect device reliability. 4. jedec standard multilayer board ? 2s2p (2 signal, 2 power) with 8 filled thermal vias under exposed pad.
nb7l72m http://onsemi.com 4 table 5. dc characteristics, multi ? level inputs v cc = 2.375 v to 3.6 v, gnd = 0 v, t a = ? 40 c to +85 c (note 5) symbol characteristic min typ max unit power supply current v cc power supply voltage v cc = 2.5 v v cc = 3.3 v 2.375 3.0 2.5 3.3 2.625 3.6 v i cc power supply current (inputs and outputs open) 80 135 175 ma cml outputs v oh output high voltage (note 6) v cc = 3.3 v v cc = 2.5 v v cc ? 40 3260 2460 v cc ? 20 3280 2480 v cc 3300 2500 mv v ol output low voltage (note 6) v cc = 3.3 v v cc = 2.5 v v cc ? 650 2650 v cc ? 600 1900 v cc ? 500 2800 v cc ? 500 2000 v cc ? 400 2900 v cc ? 350 2150 mv differential clock inputs driven single ? ended (note 7) (figures 5 and 7) v th input threshold reference voltage range (note 8) 1050 v cc ? 100 mv v ih single ? ended input high voltage v th + 100 v cc mv v il single ? ended input low voltage gnd v th ? 100 mv v ise single ? ended input voltage (v ih ? v il ) 200 2800 mv differential data/clock inputs driven differentially (figures 6 and 8) (note 9) v ihd differential input high voltage (inn, inn ) 1100 v cc mv v ild differential input low voltage (inn, inn ) gnd v cc ? 100 mv v id differential input voltage (inn, inn ) (v ihd ? v ild ) 100 1200 mv v cmr input common mode range (differential configuration, note 10) (figure 9) 950 v cc ? 50 mv i ih input high current inn, inn (vtin/vtin open) ? 150 150 a i il input low current inn, inn (vtin/vtin open) ? 150 150 a control inputs (sel0, sel1) v ih input high voltage for control pins 2.0 v cc mv v il input low voltage for control pins gnd 0.8 mv i ih input high current ? 150 150 a i il input low current ? 150 150 a termination resistors r tin internal input termination resistor 40 50 60 r tout internal output termination resistor 40 50 60 note: device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printe d circuit board with maintained transverse airflow greater than 500 lfpm. electrical parameters are guaranteed only over the declared operating temperature range. functional operation of the device exceeding these conditions is not implied. device specification limit values are applied individually under normal operating conditions and not valid simultaneously. 5. input and output parameters vary 1:1 with v cc . 6. cml outputs loaded with 50 to v cc for proper operation. 7. v th , v ih , v il,, and v ise parameters must be complied with simultaneously. 8. v th is applied to the complementary input when operating in single ? ended mode. 9. v ihd , v ild, v id and v cmr parameters must be complied with simultaneously. 10. v cmr min varies 1:1 with gnd, v cmr max varies 1:1 with v cc . the v cmr range is referenced to the most positive side of the differential input signal.
nb7l72m http://onsemi.com 5 table 6. ac characteristics v cc = 2.375 v to 3.6 v; gnd = 0 v; t a = ? 40 c to 85 c (note 11) symbol characteristic min typ max unit f max maximum input clock frequency v out 250 mv v out 200 mv 7.0 8.5 ghz f datamax maximum operating data rate (prbs23) 10 gbps v outpp output voltage amplitude (@ v inppmin ) f in 8.5 ghz (see figures 3 and 10, note 12) 200 400 mv t plh , t phl propagation delay to differential outputs, @ 1ghz, measured at differential cross ? point inn/inn to qn/qn seln to qn/qn 110 150 180 ps t plh tc propagation delay temperature coefficient 50 fs/ c t skew output ? to ? output skew (within device) (note 13) device ? to ? device skew (t pdmax ? t pdmin ) 10 20 ps t dc output clock duty cycle (reference duty cycle = 50%) f in 8.5ghz 45 50 55 % t jitter rj ? output random jitter (note 14) f in 8.5 ghz dj ? deterministic jitter (note 15) 10 gbps 0.2 0.5 10 ps rms ps pk ? pk v inpp input voltage swing (differential configuration) (note 16) 100 1200 mv t r, , t f output rise/fall times @ 1 ghz (20% ? 80%), q, q 25 30 50 ps note: device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printe d circuit board with maintained transverse airflow greater than 500 lfpm. electrical parameters are guaranteed only over the declared operating temperature range. functional operation of the device exceeding these conditions is not implied. device specification limit values are applied individually under normal operating conditions and not valid simultaneously. 11. measured using a 400 mv source, 50% duty cycle clock source. all output loading with external 50 to v cc . input edge rates 40 ps (20% ? 80%). 12. output voltage swing is a single ? ended measurement operating in differential mode. 13. skew is measured between outputs under identical transitions and conditions. duty cycle skew is defined only for dif ferential operation when the delays are measured from cross ? point of the inputs to the cross ? point of the outputs. 14. additive rms jitter with 50% duty cycle clock signal. 15. additive peak ? to ? peak data dependent jitter with input nrz data at prbs23. 16. input voltage swing is a single ? ended measurement operating in differential mode. figure 3. clock output voltage amplitude (v outpp ) vs. input frequency (f in ) at ambient temperature (typ) fin, clock input frequency (ghz) output voltage amplitude (mv) 500 450 400 350 300 200 0 1.0 2.0 3.0 4.0 5.0 6.0 7.0 8.0 q amp (mv) figure 4. input structure 50 50 v tn v cc inn inn 250
nb7l72m http://onsemi.com 6 in v th in v th figure 5. differential input driven single ? ended v ih v il v ihmax v ilmax v ih v th v il v ihmin v ilmin v cc v thmax v thmin gnd v th in in v ildmax v ihdmax v ihdtyp v ildtyp v ihdmin v ildmin v cmr gnd v id = v ihd ? v ild v cc in in q q t plh t phl v outpp = v oh (q) ? v ol (q) v inpp = v ih (in) ? v il (in) v ihd v ild v id = |v ihd(in) ? v ild(in)| in in figure 6. differential inputs driven differentially figure 7. v th diagram figure 8. differential inputs driven differentially figure 9. v cmr diagram figure 10. ac reference measurement in in v cmmax v cmmin figure 11. typical cml output structure and termination v cc 50 50 16 ma 50 50 v cc (receiver) gnd nb7l72m receiver q q
nb7l72m http://onsemi.com 7 driver device receiver device qd figure 12. typical termination for cml output driver and device evaluation q d v cc 50 50 z = 50 z = 50 dut lvpecl driver v cc gnd z o = 50 vt = v cc ? 2 v z o = 50 nb7l72m in 50 50 in gnd figure 13. lvpecl interface lvds driver v cc gnd z o = 50 v t = open z o = 50 nb7l72m in 50 50 in gnd figure 14. lvds interface v cc v cc cml driver v cc gnd z o = 50 v t = v cc z o = 50 nb7l72m in 50 50 in gnd v cc figure 15. standard 50 load cml interface differential driver v cc gnd z o = 50 vt = v refac * z o = 50 nb7l72m in 50 50 in gnd v cc figure 16. capacitor ? coupled differential interface (vt connected to external v refac ) *v refac bypassed to ground with a 0.01 f capacitor ordering information device package shipping ? nb7l72mmng qfn ? 16 (pb ? free) 123 units / rail NB7L72MMNTXG qfn ? 16 (pb ? free) 3000 / tape & reel nb7l72mmnhtbg qfn ? 16 (pb ? free) 100 / tape & reel ?for information on tape and reel specifications, including part orientation and tape sizes, please refer to our tape and reel packaging specifications brochure, brd8011/d.
nb7l72m http://onsemi.com 8 package dimensions qfn16 3x3, 0.5p case 485g issue f ??? ??? ??? ??? 16x seating plane l d e 0.10 c a a1 e d2 e2 b 1 4 8 9 16 notes: 1. dimensioning and tolerancing per asme y14.5m, 1994. 2. controlling dimension: millimeters. 3. dimension b applies to plated terminal and is measured between 0.25 and 0.30 mm from terminal. 4. coplanarity applies to the exposed pad as well as the terminals. b a 0.10 c top view side view bottom view pin 1 location 0.05 c 0.05 c (a3) c note 4 16x 0.10 c 0.05 c a b note 3 k 16x l1 detail a l alternate terminal constructions ?? *for additional information on our pb ? free strategy and soldering details, please download the on semiconductor soldering and mounting techniques reference manual, solderrm/d. recommended 2x 0.50 pitch 1.84 3.30 1 dimensions: millimeters 0.58 16x 2x 0.30 16x outline package 2x 2x 0.10 c a b e/2 soldering footprint* dim min nom max millimeters a 0.80 0.90 1.00 a1 0.00 0.03 0.05 a3 0.20 ref b 0.18 0.24 0.30 d 3.00 bsc d2 1.65 1.75 1.85 e 3.00 bsc e2 1.65 1.75 1.85 e 0.50 bsc k 0.18 typ l 0.30 0.40 0.50 l1 0.00 0.08 0.15 on semiconductor and are registered trademarks of semiconductor co mponents industries, llc (scillc). scillc owns the rights to a numb er of patents, trademarks, copyrights, trade secrets, and other intellectual property. a list ing of scillc?s product/patent coverage may be accessed at ww w.onsemi.com/site/pdf/patent ? marking.pdf. scillc reserves the right to make changes without further notice to any products herein. scillc makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does scillc assume any liability arising out of the application or use of any product or circuit, and s pecifically disclaims any and all liability, including without limitation special, consequential or incidental damages. ?typical? parameters which may be provided in scillc data sheets and/ or specifications can and do vary in different applications and actual performance may vary over time. all operating parame ters, including ?typicals? must be validated for each customer application by customer?s technical experts. scillc does not convey any license under its patent rights nor the right s of others. scillc products are not designed, intended, or a uthorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in whic h the failure of the scillc product could create a situation where personal injury or death may occur. should buyer purchase or us e scillc products for any such unintended or unauthorized appli cation, buyer shall indemnify and hold scillc and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unin tended or unauthorized use, even if such claim alleges that scil lc was negligent regarding the design or manufacture of the part. scillc is an equal opportunity/affirmative action employer. this literature is subject to all applicable copyrig ht laws and is not for resale in any manner. publication ordering information n. american technical support : 800 ? 282 ? 9855 toll free usa/canada europe, middle east and africa technical support: phone: 421 33 790 2910 japan customer focus center phone: 81 ? 3 ? 5817 ? 1050 nb7l72m/d gigacomm is a trademark of semiconductor components industries, llc (scillc). literature fulfillment : literature distribution center for on semiconductor p.o. box 5163, denver, colorado 80217 usa phone : 303 ? 675 ? 2175 or 800 ? 344 ? 3860 toll free usa/canada fax : 303 ? 675 ? 2176 or 800 ? 344 ? 3867 toll free usa/canada email : orderlit@onsemi.com on semiconductor website : www.onsemi.com order literature : http://www.onsemi.com/orderlit for additional information, please contact your local sales representative
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